The invention relates to a fractional spaced equalizer (FSEQ) having adjustable coefficients for equalizing a reception signal of a transceiver, and to a method for setting said coefficients of said fractional spaced equalizer.
FIG. 1 shows a data transmission system according to the state of the art. The data transmission system includes transceivers which are connected to each other via a data transmission channel formed by a transmission line. Each transceiver includes a data transmitting signal path and a data reception signal path. The data transmission line is used in the normal operation mode for the transmission of data in both directions at the same time, i.e. downstream and upstream. The transceiver receives transmission data from a data source. The transmission signal path of the transceiver comprises an encoder for encoding the transmission data and a transmission filter for filtering the encoded data. The filtered transmission data is digital-analog converted by a digital-analog converter and forwarded to a hybrid circuit. The analog transmission signal is sent to the receiving transceiver via the data transmission line and forwarded to the transceiver on the other side of the data transmission line. The receiver of each transceiver comprises an analog-digital converter, a digital reception filter and an interpolator for the interpolation of the filter reception signal. The received signal is converted from analog to digital, is filtered and afterwards sampled within the receiver. An estimated value determined by an echo compensator EC is then subtracted from the sampled received signal. The echo compensator EC is provided for compensating an echo signal caused by the transmitter within a transceiver when transmitting data via the data transmission line to the distant transceiver. A difference signal between the estimated value and the output signal of the interpolator is passed to an equalizer EQ. The output of the equalizer EQ is forwarded to a decision unit which decides on the received data symbols. The reception data output by the decision unit is output to a data sink. A timing error detection unit connected to the input and to the output of the decision unit generates a phase control criterium signal supplied to a clock recovery unit. The clock recovery unit regulates the sampling phase φ of the interpolator to synchronize the sampling frequency to a transmitter symbol frequency.
The echo compensator EC is normally formed by a digital adaptive FIR-filter wherein the coefficients of the filter are adjusted depending on the output signal of the subtractor, i.e. the difference signal between the output signal of the interpolator and the estimated value generated by the echo compensator. The output of the decision unit is normally fed-back via a decision feedback equalizing circuit to the input of the decision unit as shown in FIG. 1.
FIG. 2 shows a timing diagram of a digital reception signal as received by a conventional receiver as shown in FIG. 1. The analog-digital converter samples the received analog signal with a free-running sample frequency sample. The sample filter is filtered by the reception filter and then interpolated by the interpolator. By using a predetermined number of samples, the interpolator interpolates an interpolated value as shown in FIG. 2 wherein the sampling phase φT is set by the clock recovery unit in response to the phase control criterium generated by the timing error detector. The interpolated value is output by the interpolator to a subtractor which subtracts the estimated value output by the echo compensator EC. A difference signal is filtered by the equalizer EQ which is a linear equalizer normally formed by an FIR-filter. The filtered difference values form the basis for the decision performed by the decision unit which compares the received values with a threshold value to decide which value has probably been sent by the transceiver on the other side of the data transmission line.
FIG. 3 shows the digital signal at the input of the equalizer EQ and on the output of said equalizer EQ. By providing the linear equalizer EQ, it is possible to minimize the precursors of the impulse response as can be seen in FIG. 3B. However, the postcursors are not minimized. By the provision of the decision feedback equalizer, the input signal applied to the decision unit approaches almost an ideal impulse response wherein also the postcursors are minimized to zero.
FIG. 4 shows the time signal to illustrate a training phase as used in an SHDL data transmission system according to the state of the art. At the start of the setting-up of a data connection between the transceivers TA and TB a training signal is transmitted during a training phase. The training phase comprises a training phase I wherein data is transmitted in a half-duplex mode and a training phase II wherein data is ex-changed between both transceivers TA, TB in a full-duplex mode. A test or training signal is defined for a period of one or two seconds depending on the data transmission rate. During training phase I the first one of the transceivers, i.e. the transceiver TA, is transmitting data via the data transmission line to the distant transceiver, i.e. transceiver TB, and subsequently the transceiver TB transmits data back via the data transmission line to the first transceiver TA. During training phase I, the receiver at the remote end of the data transmission line receives only the transmission signal from the opposite end, but not the echo signal generated by its own transmitter. In a transceiver according to the SHDSL-standard, training phase I is not used to adjust coefficients within filters of the transceiver. The setting of the coefficients is performed during training phase II as shown in FIG. 4. After the setting of the coefficients, data is exchanged between both transceivers TA, TB during a data transmission phase in a full-duplex mode.
Returning to FIG. 1 showing a transceiver according to the state of the art, the equalizer EQ can be formed by the so-called T-equalizer operating at symbol frequency fT or by a
      T    2    -  equalizeroperating at twice the symbol frequency. Depending on the equalizer, the symbol frequency fT or twice the symbol frequency is chosen as the sampling frequency. In both cases, the sampling phase fT is regulated, since the sampling frequency has to be synchronized to the transmitter symbol frequency.
Originally, T-equalizers have been used operating at symbol frequency fT. However, T-equalizers have the disadvantage that the achievable signal-to-noise ratio SNR after the equalization process depends on the precise sampling phase φT. There is no regulating criterium to achieve a maximum signal-to-noise ratio at an optimal sampling phase φT. Accordingly, transceivers comprising a T-equalizer EQ show an increased bit error rate BER, since the maximum signal-to-noise ratio SNRmax cannot be achieved. There are even poor sampling phases in which the correct synchronization of the receiver comprising a T-equalizer is completely impossible.
As a consequence, transceivers according to the state of the art have been proposed including
      T    2    -  equalizerswhich are largely independent of the precise sampling phase.
The
      T    2    -  equalizerhas a signal-to-noise ratio SNR which is almost constant for all sampling phases. If the
      T    2    -  equalizerEQ is designed appropriately, this also generally results in a somewhat better noise response depending on the noise signal, the transmission line as well as the transmission and the reception filters. Since the signal values at the output of the equalizer EQ always have to be calculated only in time with the signal clock, the implementation complexity for the
      T    2    -  equalizercorresponds approximately to the implementation complexity of the T-equalizer EQ provided that the number of coefficients are used as the basis in both cases and that a digital non-recursive filter is used in each case.
However, when using a
      T    2    -  equalizerwithin the transceiver, the digital input values supplied to that equalizer have to be provided at twice the sampling frequency. Accordingly, all circuits which are arranged upstream of the
      T    2    -  equalizerEQ have to provide digital values at twice the sampling frequency increasing the complexity of all circuits which are arranged upstream of the equalizer EQ. The input signal of the
      T    2    -  equalizerEQ is formed by the difference between the reception signal and the echo signal generated by the echo compensator EC. Accordingly, the implementation complexity in particular of the echo compensator EC is thus literally twice as great when using a
      T    2    -  equalizerEQ instead of a T-equalizer. When using a
      T    2    -  equalizerEQ, the echo compensator EC has to calculate twice the number of echo values so that the number of coefficients implemented within the echo compensator EC is doubled in comparison with an echo compensator EC within a transceiver having a T-equalizer.
Consequently, the overall implementation complexity of a transceiver having a
      T    2    -  equalizeris considerably greater than that of a transceiver including the T-equalizer EQ. An echo compensator EC is a complex circuit comprising typically 150 coefficients. When using the
            T      2        -    equalizer    ,the number of more than 150 coefficients has to be doubled to more than 300 coefficients, thus increasing the overall implementation complexity of the transceiver considerably.
Because of this reason conventional transceivers included T-equalizers EQ although they diminish the performance of the transceiver.